; vim: sts=4 sw=8 et ai fdm=marker ft=asm

.nolist
.include "m8def.inc"
.list
.include "fifo_handling.inc"


;   compile settings
; =============================================================================
; SERIALDEBUG    ; define SERIALDEBUG for extra debugging output



;   flags and aliases
; =============================================================================

; serial port
.equ CLOCK = 4000000
.equ BAUD = 19200
.equ UBRRVAL = CLOCK/(BAUD*16)-1

; timer1 loop, half a second with prescaler 256
.equ HALFSECOND = CLOCK/(256*2)

; leds
.equ STATUSLED = 0
.equ UARTLED = 1
.equ TWILED = 2

; fifo sizes
.equ URSize = 255        ; uart receive fifo size
.equ UTSize = 128        ; uart transmit fifo size
.equ IRSize = 64         ; i2c receive fifo size
.equ ITSize = 255        ; i2c transmit fifo size

; twi
.equ TWICommandByteSize = 5 ; one twi command is 1 byte address and 4 byte data
.equ ADDR = 0b1000000 ; own twi address
.equ GCE = 1             ; general call enabled

; global flags
.equ TWITransmission = 0 ; if bit0 is set, a twi transmission is active


;   fifos {{{
; =============================================================================
.dseg
        ;   fifo: UReceiveFifo
        ; ==========================
        UReceiveFifo:
            .byte   FifoControlSize + URSize

        ;   fifo: UTransmitFifo
        ; ==========================
        UTransmitFifo:
            .byte   FifoControlSize + UTSize

        ;   fifo: IReceiveFifo
        ; ==========================
        IReceiveFifo:
            .byte   FifoControlSize + IRSize

        ;   fifo: ITransmitFifo
        ; ==========================
        ITransmitFifo:
            .byte   FifoControlSize + ITSize

.cseg
; }}}

;   register definitions
; =============================================================================
.def    l1      =   r8      ; low working registers
.def    l2      =   r9
.def    TD1     =   r10
.def    w1      =   r16     ; working registers
.def    w2      =   r17
.def    w3      =   r18
.def    w4      =   r19
.def    Flags   =   r20     ; globa flags
.def    TWIDC   =   r21     ; twi data counter register


;   interrupt table {{{
; =============================================================================
.ORG 0x0                            ; reset vector
        rjmp reset

.ORG OC1Aaddr                       ; timer1 CompareA interrupt handler
        rjmp OC1AHandler
.ORG URXCaddr                       ; USART receive complete interrupt handler
        rjmp URXCHandler
.ORG UDREaddr                       ; USART data register empty handler
        rjmp UDREHandler
.ORG TWIaddr                        ; TWI data handler
        rjmp TWIHandler
.ORG INT_VECTORS_SIZE               ; program start

; }}}

;   SERIALDEBUG output routines {{{
; =============================================================================

;   DEBUG_write_uart_transmit_fifo {{{
; =============================================================================
; saves registers and calls write_uart_transmit_fifo
DEBUG_write_uart_transmit_fifo:
        push w2
        push l1
        push l2
        rcall write_uart_transmit_fifo
        pop l2
        pop l1
        pop w2
        ret
; }}}

; writes an immediate value
.macro DEBUG_WRITE_I
.ifdef SERIALDEBUG
    push w1
    ldi w1, @0
    rcall DEBUG_write_utf
    pop w1
.endif
.endmacro

; writes an register value
.macro DEBUG_WRITE_R
.ifdef SERIALDEBUG
    push w1
    mov w1, @0
    rcall DEBUG_write_utf
    pop w1
.endif
.endmacro

; }}}

;   function: reset interrupt handler {{{
; =============================================================================
reset:

        ;  init stack
        ; ========================================
        ldi w1, low(RAMEND)
        out SPL, w1
        ldi w1, high(RAMEND)
        out SPH, w1

        ;  init uart
        ; ========================================
        ldi w1, high(UBRRVAL)
        out UBRRH, w1
        ldi w1, low(UBRRVAL)
        out UBRRL, w1
        ldi w1, (1<<URSEL)|(3<<UCSZ0) ; frame format: 8N1
        out UCSRC, w1

        ;  init fifos
        ; ========================================
        MACRO_FIFO_INIT UReceiveFifo
        MACRO_FIFO_INIT UTransmitFifo
        MACRO_FIFO_INIT IReceiveFifo
        MACRO_FIFO_INIT ITransmitFifo

        ;  enable uart interrupt
        ; ========================================
        ldi w1, (1<<RXCIE)|(1<<RXEN)|(1<<TXEN); receiver interrupt complete enable, receiver enable,
                                        ; transmitter enable
        out UCSRB, w1

        ;  init and enable twr
        ; ========================================
        ldi w1, 255                     ; bitrate
        out TWBR, w1
        ldi w1, 0                       ; no prescaler
        out TWSR, w1
        ldi w1, (ADDR<<1)|(GCE)      ; set address (7bit) and general call enable (1bit)
        out TWAR, w1
        ldi w1, (1<<TWEN)|(1<<TWINT)|(1<<TWIE)|(1<<TWEA) ; twi enable, twi interrupt clearance,
                                                         ; twi interrupt enable, twi enable ack
        out TWCR, w1

        ;  init led output
        ; ========================================
        ldi w1, 0b111                   ; use PB0-PB2 as output
        out DDRB, w1

        in w1, PORTB                    ; switch leds off
        ori w1, 0b111
        out PORTB, w1

        ;  init timer1
        ; ========================================
        ldi w1, high(HALFSECOND)         ; initial delay before loop starts
        out OCR1AH, w1
        ldi w1, low(HALFSECOND)
        out OCR1AL, w1

        ldi w1, (1<<CS12)|(1<<WGM12) ; prescaler 256, clear timer1 on overflow
        out TCCR1B, w1
        clr w1                      ; nothing else
        out TCCR1A, w1

        ldi w1, (1<<OCIE1A)         ; enable timer1 compare interrupt
        out TIMSK, w1

        ;  reset flags
        ; ========================================
        ldi Flags, 0
        ldi TWIDC, 0

        ;  enable interrupts
        ; ========================================
        sei

        ;  output system bootup message to uart
        ; ========================================
        rcall output_string
        .db "bc", 0, 0

        ;  start main procedure
        ; ========================================
        rjmp main

; }}}


;   function: uart receive complete interrupt handler {{{
; =============================================================================
URXCHandler:
        push w1                     ; save w1
        in w1, SREG                 ; save the status register
        push w1

        MACRO_FIFO_LOAD_COUNTER UReceiveFifo, w1 ; load counter
        cpi w1, URSize              ; compare counter and fifo size
        breq URXDiscardData         ; if counter == fifosize, just discard the byte received  1 false/2 true

        push YL                     ; save Y
        push YH

        in YL, PORTB                ; announce uart traffic by toggling led
        ldi YH, (1<<UARTLED)
        eor YL, YH
        out PORTB, YL

        in w1, UDR                  ; read data byte

        push w2
                                    ; store data into receive fifo
        MACRO_FIFO_STORE UReceiveFifo, w1, w2, URSize
        pop w2

URXCleanup:
        pop YH                      ; restore Y
        pop YL
        pop w1                      ; restore the status register
        out SREG, w1
        pop w1                      ; restore w1
        reti

URXDiscardData:
        in w1, UDR                  ; clear interrupt by reading the received byte
        pop w1                      ; restore the status register
        out SREG, w1
        pop w1                      ; restore w1
        reti

; }}}

;   function: uart data register empty handler {{{
; =============================================================================
UDREHandler:
        push w1                     ; save w1
        in w1, SREG                 ; save the status register
        push w1

                                    ; load uart transmit fifo counter into w1
        MACRO_FIFO_LOAD_COUNTER UTransmitFifo, w1
        cpi w1, 1                   ; if there are any bytes left to be transmit
        brsh UDRETransmitByte       ;   do it
                                    ; else:
        cbi UCSRB, UDRIE            ;   disable this interrupt(this is a low register)
        sei
        pop w1                      ; restore the status register
        out SREG, w1
        pop w1                      ; restore w1
        reti

UDRETransmitByte:
        push YL                     ; save Y
        push YH

        MACRO_FIFO_READ UTransmitFifo, w1, UTSize
        out UDR, w1                 ; write data to uart data register

        sei                         ; allow recursive interrupts

        pop YH                      ; restore Y
        pop YL
        pop w1                      ; restore the status register
        out SREG, w1
        pop w1                      ; restore w1
        reti
; }}}

;   function: TWI interrupt handler {{{
;
; =============================================================================
TWIHandler:
        push w1                     ; save registers
        in w1, SREG
        push w1
        push w2
        push w3

        in w1, PORTB                ; announce twi traffic by toggling led
        ldi w2, (1<<TWILED)
        eor w1, w2
        out PORTB, w1

        DEBUG_WRITE_I 'T'

        in w1, TWSR                 ; load the status code
        andi w1, 0b11111000         ; masq away prescaler bits

        DEBUG_WRITE_R w1

        cpi w1, 0x08                ; start transmitted
        breq TWI_start
        cpi w1, 0x10                ; repeated start transmitted
        breq TWI_start
        cpi w1, 0x18                ; sla+w transmitted, ack
        breq TWI_sla_w_ack
        cpi w1, 0x20                ; sla+w transmitted, nack
        breq TWI_sla_w_nack
        cpi w1, 0x28                ; data transmitted, ack
        breq TWI_data_transmit_ack
        cpi w1, 0x30                ; data transmitted, nack
        breq TWI_data_transmit_nack
        cpi w1, 0x38                ; sla+w or data transmitted, abitration lost
        breq TWI_abitration_lost

        cpi w1, 0                   ; bus error
        brne TWI_error

        DEBUG_WRITE_R w1

TWI_error:
        .ifdef SERIALDEBUG
                ldi w1, 'E'
                rcall write_uart_transmit_fifo
                ldi w1, 'e'
                rcall write_uart_transmit_fifo

                ldi w1, 'F'
                rcall write_uart_transmit_fifo
                ldi w1, 'n'
                rcall write_uart_transmit_fifo
                ldi w1, 'o'
                rcall write_uart_transmit_fifo
                ldi w1, 'r'
                rcall write_uart_transmit_fifo
                ldi w1, 'd'
                rcall write_uart_transmit_fifo
        .endif

        cbr Flags, TWITransmission      ; clear transmission active flag
        ldi w1, (1<<TWINT)|(1<<TWSTO)
        out TWCR, w1

        rjmp TWI_cleanup

TWI_unhandled:
        DEBUG_WRITE_I 'X'

        rjmp TWI_abort

TWI_start:
        DEBUG_WRITE_I 'A'

        sbr Flags, (1<<TWITransmission) ; set transmission active flag

        rcall read_i2c_transmit_fifo    ; read data byte counter
        mov TWIDC, w1                   ; copy to register

        rcall read_i2c_transmit_fifo    ; read slave address and write bit
        out TWDR, w1                ; output slave address and write bit to data register

        DEBUG_WRITE_R w1

        in w1, TWCR                 ; clear TWSTA and TWSTO
        cbr w1, (1<<TWSTA)|(1<<TWSTO)
        out TWCR, w1

        rjmp TWI_next_command

TWI_sla_w_ack:
        dec TWIDC                       ; decrement twi data counter

        rcall read_i2c_transmit_fifo    ; and read data byte and output to data register
        out TWDR, w1

        dec TWIDC                       ; decrement data counter

        DEBUG_WRITE_I 'D'
        DEBUG_WRITE_R TWIDC

        cpi TWIDC, 0                  ; check if we have some bytes left
        breq TWI_send_data_finished     ; if there is no data left, finish transfer

        rjmp TWI_next_command

TWI_sla_w_nack:
        in w1, TWCR
        ori w1, (1<<TWINT)|(1<<TWSTO)
        out TWCR, w1

    TWI_sla_w_nack_loop:
        rcall read_i2c_transmit_fifo
        dec TWIDC
        brne TWI_sla_w_nack_loop

        cbr Flags, (1<<TWITransmission) ; clear transmission active flag

        ; FIXME? > . . . . \
                ldi w1, 'N'
                rcall write_uart_transmit_fifo
        .ifdef SERIALDEBUG
                ldi w1, 0
                rcall write_uart_transmit_fifo
        .endif

        rjmp TWI_cleanup

TWI_data_transmit_ack:
        cpi TWIDC, 0
        breq TWI_send_data_finished     ; if there is no data left, finish transfer


        DEBUG_WRITE_I 'D'
        DEBUG_WRITE_R TWIDC

        rcall read_i2c_transmit_fifo    ; else read data byte and output to data register
        out TWDR, w1

        dec TWIDC                       ; decrement data counter

        rjmp TWI_next_command

TWI_data_transmit_nack:
    TWI_data_transmit_nack_loop:
        rcall read_i2c_transmit_fifo
        dec TWIDC
        brne TWI_data_transmit_nack_loop

        rjmp TWI_send_data_finished

TWI_abitration_lost:
    TWI_abitration_lost_loop:
        rcall read_i2c_transmit_fifo
        dec TWIDC
        brne TWI_abitration_lost_loop

        rjmp TWI_abort

TWI_send_data_finished:
        ; FIXME?> . . . . \
                ldi w1, 'F'
                rcall write_uart_transmit_fifo
        .ifdef SERIALDEBUG
                mov w1, TWIDC
                rcall write_uart_transmit_fifo
        .endif

        in w1, TWCR                 ; generate stop signal
        ori w1, (1<<TWINT)|(1<<TWSTO)
        out TWCR, w1

        cbr Flags, (1<<TWITransmission) ; clear transmission active flag

        rjmp TWI_cleanup

TWI_abort:
        cbr Flags, (1<<TWITransmission) ; clear transmission active flag
        ldi w1, (1<<TWINT)|(1<<TWEN)|(1<<TWIE)|(1<<TWEA)
        out TWCR, w1
        rjmp TWI_cleanup

TWI_next_command:
        in w1, TWCR                 ; initiate next twi command
        ori w1, (1<<TWINT)
        out TWCR, w1

TWI_cleanup:
        pop w3                      ; restore registers
        pop w2
        pop w1
        out SREG, w1
        pop w1
        reti

; }}}

;   function: timer1 interrupt handler {{{
;
; =============================================================================
OC1AHandler:
        push w1                     ; save registers
        in w1, SREG
        push w1
        push w2

        in w1, PORTB                ; toggle statusled
        ldi w2, (1<<STATUSLED)
        eor w1, w2
        ori w1, (1<<UARTLED)        ; switch off uartled
        out PORTB, w1

        pop w2                      ; restore registers
        pop w1
        out SREG, w1
        pop w1
        reti
; }}}




;   function: main
; =============================================================================
main:
        rcall check_serial_input

        MACRO_FIFO_LOAD_COUNTER ITransmitFifo, w1    ; if more than 5 bytes
        cpi w1, 6
        brsh main_start_transmission

        rjmp main

main_start_transmission:
        sbrc Flags, TWITransmission        ; start transmission if none active
        rjmp main

        sbr Flags, (1<<TWITransmission)    ; set transmission active flag

        DEBUG_WRITE_I 'I'
        DEBUG_WRITE_R Flags

        ldi w1, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)|(1<<TWIE) ; generate start signal
        out TWCR, w1

        rjmp main



;   function: check_serial_input {{{
; =============================================================================
check_serial_input:
        MACRO_FIFO_LOAD_COUNTER UReceiveFifo, w1   ; load uart receive fifo counter into w1
        cpi w1, 6
        brsh check_prepare ; if not, return

        ret

    check_prepare:
        MACRO_FIFO_READ UReceiveFifo, w1, URSize   ; else load byte counter into w1
        MACRO_FIFO_STORE ITransmitFifo, w1, w2, ITSize ; and store it again.

    check_loop:
        MACRO_FIFO_READ UReceiveFifo, w2, URSize   ; else load byte into w2
        MACRO_FIFO_STORE ITransmitFifo, w2, w3, ITSize ; and store it again.

        dec w1
        brne check_loop ; while nonzero, loop

        ret
; }}}

;   function: write_uart_transmit_fifo {{{
; =============================================================================
; data byte is loaded into w1
write_uart_transmit_fifo:
        MACRO_FIFO_LOAD_COUNTER UTransmitFifo, w2   ; load uart transmit fifo counter into w2
        cpi w2, UTSize ; compare counter and fifo size
        breq write_uart_discard_data ; if counter == fifosize, just discard the byte received

        movw l2:l1, YH:YL           ; save Y

        MACRO_FIFO_STORE UTransmitFifo, w1, w2, UTSize
        sbi UCSRB, UDRIE            ; enable data register empty interrupt
        movw YH:YL, l2:l1           ; restore Y

write_uart_discard_data:

        ret
; }}}

;   function: output_string {{{
; =============================================================================
output_string:
        pop ZH              ; load string address from the stack
        pop ZL
        lsl ZL              ; shift left Z (using carry)
        rol ZH
output_next_char:
        lpm w1, Z+          ; load next byte into w1 and increment Z
        cpi w1, 0           ; if it's not the end of the string
        breq output_string_end ; jump away

        rcall write_uart_transmit_fifo ; transmit char

        rjmp output_next_char ; loop

output_string_end:
        adiw ZL, 1          ; increment Z to point to the next instruction after the string
        lsr ZH              ; shift right Z (using carry)
        ror ZL
        push ZL             ; push Z back onto the stack
        push ZH
        ret

; }}}


;   function: check_twi_status {{{
; =============================================================================
check_twi_status:
        MACRO_FIFO_LOAD_COUNTER IReceiveFifo, w1 ; load counter

        cpi w1, 0           ; if no data has been received, return
        breq check_twi_end

        ;rcall output_string
        ;.db "r: ", 0, 0

        ;rcall read_i2c_receive_fifo ; read received statuscode

        ;rcall write_uart_transmit_fifo  ; output char

        ;ldi w1, 10
        ;rcall write_uart_transmit_fifo  ; output char
        ;ldi w1, 13
        ;rcall write_uart_transmit_fifo  ; output char


check_twi_end:
        ret
; }}}


;   function: read_i2c_receive_fifo {{{
; =============================================================================
; uses: w1, Y
; databyte: w1

read_i2c_receive_fifo:
        MACRO_FIFO_READ IReceiveFifo, w1, IRSize
        ret

; }}}

;   function: store_i2c_receive_fifo {{{
; =============================================================================
; uses: w2, Y
; databyte: w1

store_i2c_receive_fifo:
        MACRO_FIFO_STORE IReceiveFifo, w1, w2, IRSize
        ret

; }}}

;   function: read_i2c_transmit_fifo {{{
; =============================================================================
; uses: w1, Y
; databyte: w1

read_i2c_transmit_fifo:
        MACRO_FIFO_READ ITransmitFifo, w1, ITSize
        ret

; }}}

;   function: store_i2c_transmit_fifo {{{
; =============================================================================
; uses: w2, Y
; databyte: w1

store_i2c_transmit_fifo:
        MACRO_FIFO_STORE ITransmitFifo, w1, w2, ITSize
        ret

; }}}